CMOS imager with a self-aligned buried contact

ABSTRACT

An imaging device formed as a CMOS semiconductor integrated circuit includes a buried contact line between the floating diffusion region and the gate of a source follower output transistor. The self-aligned buried contact in the CMOS imager decreases leakage from the diffusion region into the substrate which may occur with other techniques for interconnecting the diffusion region with the source follower transistor gate. Additionally, the self-aligned buried contact is optimally formed between the floating diffusion region and the source follower transistor gate which allows the source follower transistor to be placed closer to the floating diffusion region, thereby allowing a greater photo detection region in the same sized imager circuit.

FIELD OF THE INVENTION

[0001] The invention relates generally to improved semiconductor imagingdevices and in particular to a silicon imaging device which can befabricated using a standard CMOS process. Particularly, the inventionrelates to CMOS imager having a self-aligned buried contact formedbetween a pair of transistor gates or a transistor gate and an isolationregion.

DISCUSSION OF RELATED ART

[0002] There are a number of different types of semiconductor-basedimagers, including charge coupled devices (CCDs), photodiode arrays,charge injection devices and hybrid focal plane arrays. CCDs are oftenemployed for image acquisition and enjoy a number of advantages whichmakes it the incumbent technology, particularly for small size imagingapplications. CCDs are also capable of large formats with small pixelsize and they employ low noise charge domain processing techniques.However, CCD imagers also suffer from a number of disadvantages. Forexample, they are susceptible to radiation damage, they exhibitdestructive read out over time, they require good light shielding toavoid image smear and they have a high power dissipation for largearrays. Additionally, while offering high performance, CCD arrays aredifficult to integrate with CMOS processing in part due to a differentprocessing technology and to their high capacitances, complicating theintegration of on-chip drive and signal processing electronics with theCCD array. While there has been some attempts to integrate on-chipsignal processing with the CCD array, these attempts have not beenentirely successful. CCDs also must transfer an image by line chargetransfers from pixel to pixel, requiring that the entire array be readout into a memory before individual pixels or groups of pixels can beaccessed and processed. This takes time. CCDs may also suffer fromincomplete charge transfer from pixel to pixel during charge transferwhich also results in image smear.

[0003] Because of the inherent limitations in CCD technology, there isan interest in CMOS imagers for possible use as low cost imagingdevices. A fully compatible CMOS sensor technology enabling a higherlevel of integration of an image array with associated processingcircuits would be beneficial to many digital applications such as, forexample, in cameras, scanners, machine vision systems, vehiclenavigation systems, video telephones, computer input devices,surveillance systems, auto focus systems, star trackers, motiondetection systems, image stabilization systems and data compressionsystems for high-definition television.

[0004] The advantages of CMOS imagers over CCD imagers are that CMOSimagers have a low voltage operation and low power consumption; CMOSimagers are compatible with integrated on-chip electronics (controllogic and timing, image processing, and signal conditioning such as A/Dconversion); CMOS imagers allow random access to the image data; andCMOS imagers have lower fabrication costs as compared with theconventional CCD since standard CMOS processing techniques can be used.Additionally, low power consumption is achieved for CMOS imagers becauseonly one row of pixels at a time needs to be active during the readoutand there is no charge transfer (and associated switching) from pixel topixel during image acquisition. On-chip integration of electronics isparticularly advantageous because of the potential to perform manysignal conditioning functions in the digital domain (versus analogsignal processing) as well as to achieve a reduction in system size andcost.

[0005] A CMOS imager circuit includes a focal plane array of pixelcells, each one of the cells including either a photogate, a photodiode,or a photoconductor overlying a substrate for accumulatingphoto-generated charge in the underlying portion of the substrate. Areadout circuit is connected to each pixel cell and includes at least anoutput field effect transistor formed in the substrate and a chargetransfer section formed on the substrate adjacent the photogate,photodiode, or the photoconductor having a sensing node, typically afloating diffusion node, connected to the gate of an output transistor.The imager may include at least one electronic device such as atransistor for transferring charge from the underlying portion of thesubstrate to the floating diffusion node and one device, also typicallya transistor, for resetting the node to a predetermined charge levelprior to charge transference.

[0006] In a CMOS imager, the active elements of a pixel cell perform thenecessary functions of: (1) photon to charge conversion; (2)accumulation of image charge; (3) transfer of charge to the floatingdiffusion node accompanied by charge amplification; (4) resetting thefloating diffusion node to a known state before the transfer of chargeto it; (5) selection of a pixel for readout; and (6) output andamplification of a signal representing pixel charge. Photo charge may beamplified when it moves from the initial charge accumulation region tothe floating diffusion node. The charge at the floating diffusion nodeis typically converted to a pixel output voltage by a source followeroutput transistor. The photosensitive element of a CMOS imager pixel istypically either a depleted p-n junction photodiode or a field induceddepletion region beneath a photogate or a photoconductor. Forphotodiodes, image lag can be eliminated by completely depleting thephotodiode upon readout.

[0007] CMOS imagers of the type discussed above are generally known asdiscussed, for example, in Nixon et al., “256×256 CMOS Active PixelSensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol.31(12) pp. 2046-2050, 1996; Mendis et al, “CMOS Active Pixel ImageSensors,” IEEE Transactions on Electron Devices, Vol. 41(3) pp. 452-453,1994 as well as U.S. Pat. No. 5,708,263 and U.S. Pat. No. 5,471,515,which are herein incorporated by reference.

[0008] To provide context for the invention, an exemplary CMOS imagingcircuit is described below with reference to FIG. 1. The circuitdescribed below, for example, includes a photogate for accumulatingphoto-generated charge in an underlying portion of the substrate. Itshould be understood that the CMOS imager may include a photodiode orother image to charge converting device, in lieu of a photogate, as theinitial accumulator for photo-generated charge.

[0009] Reference is now made to FIG. 1 which shows a simplified circuitfor a pixel of an exemplary CMOS imager using a photogate and having apixel photodetector circuit 14 and a readout circuit 60. It should beunderstood that while FIG. 1 shows the circuitry for operation of asingle pixel, that in practical use there will be an M×N array of pixelsarranged in rows and columns with the pixels of the array accessed usingrow and column select circuitry, as described in more detail below.

[0010] The photodetector circuit 14 is shown in part as across-sectional view of a semiconductor substrate 16 typically a p-typesilicon, having a surface well of p-type material 20. An optional layer18 of p-type material may be used if desired, but is not required.Substrate 16 may be formed of, for example, Si, SiGe, Ge, and GaAs.Typically the entire substrate 16 is p-type doped silicon substrate andmay contain a surface p-well 20 (with layer 18 omitted), but many otheroptions are possible, such as, for example p on p− substrates, p on p+substrates, p-wells in n-type substrates or the like. The terms wafer orsubstrate used in the description includes any semiconductor-basedstructure having an exposed surface in which to form the circuitstructure used in the invention. Wafer and substrate are to beunderstood as including, silicon-on-insulator (SOI) technology,silicon-on-sapphire (SOS) technology, doped and undoped semiconductors,epitaxial layers of silicon supported by a base semiconductorfoundation, and other semiconductor structures. Furthermore, whenreference is made to a wafer or substrate in the following description,previous process steps may have been utilized to form regions/junctionsin the base semiconductor structure or foundation.

[0011] An insulating layer 22 such as, for example, silicon dioxide isformed on the upper surface of p-well 20. The p-type layer may be ap-well formed in substrate 16. A photogate 24 thin enough to passradiant energy or of a material which passes radiant energy is formed onthe insulating layer 22. The photogate 24 receives an applied controlsignal PG which causes the initial accumulation of pixel charges in n+region 26. The n+ type region 26, adjacent one side of photogate 24, isformed in the upper surface of p-well 20. A transfer gate 28 is formedon insulating layer 22 between n+ type region 26 and a second n+ typeregion 30 formed in p-well 20. The n+ regions 26 and 30 and transfergate 28 form a charge transfer transistor 29 which is controlled by atransfer signal TX. The n+ region 30 is typically called a floatingdiffusion region. It is also a node for passing charge accumulatedthereat to the gate of a source follower transistor 36 described below.A reset gate 32 is also formed on insulating layer 22 adjacent andbetween n+ type region 30 and another n+ region 34 which is also formedin p-well 20. The reset gate 32 and n+ regions 30 and 34 form a resettransistor 31 which is controlled by a reset signal RST. The n+ typeregion 34 is coupled to voltage source VDD. The transfer and resettransistors 29, 31 are n-channel transistors as described in thisimplementation of a CMOS imager circuit in a p-well. It should beunderstood that it is possible to implement a CMOS imager in an n-wellin which case each of the transistors would be p-channel transistors. Itshould also be noted that while FIG. 1 shows the use of a transfer gate28 and associated transistor 29, this structure provides advantages, butis not required.

[0012] Photodetector circuit 14 also includes two additional n-channeltransistors, source follower transistor 36 and row select transistor 38.Transistors 36, 38 are coupled in series, source to drain, with thesource of transistor 36 also coupled over lead 40 to voltage source VDDand the drain of transistor 38 coupled to a lead 42. The drain of rowselect transistor 38 is connected via conductor 42 to the drains ofsimilar row select transistors for other pixels in a given pixel row. Aload transistor 39 is also coupled between the drain of transistor 38and a voltage source VSS. Transistor 39 is kept on by a signal VLNapplied to its gate.

[0013] The imager includes a readout circuit 60 which includes a signalsample and hold (S/H) circuit including a S/H n-channel field effecttransistor 62 and a signal storage capacitor 64 connected to the sourcefollower transistor 36 through row transistor 38. The other side of thecapacitor 64 is connected to a source voltage VSS. The upper side of thecapacitor 64 is also connected to the gate of a p-channel outputtransistor 66. The drain of the output transistor 66 is connectedthrough a column select transistor 68 to a signal sample output nodeVOUTS and through a load transistor 70 to the voltage supply VDD. Asignal called “signal sample and hold” (SHS) briefly turns on the S/Htransistor 62 after the charge accumulated beneath the photogateelectrode 24 has been transferred to the floating diffusion node 30 andfrom there to the source follower transistor 36 and through row selecttransistor 38 to line 42, so that the capacitor 64 stores a voltagerepresenting the amount of charge previously accumulated beneath thephotogate electrode 24.

[0014] The readout circuit 60 also includes a reset sample and hold(S/H) circuit including a S/H transistor 72 and a signal storagecapacitor 74 connected through the S/H transistor 72 and through the rowselect transistor 38 to the source of the source follower transistor 36.The other side of the capacitor 74 is connected to the source voltageVSS. The upper side of the capacitor 74 is also connected to the gate ofa p-channel output transistor 76. The drain of the output transistor 76is connected through a p-channel column select transistor 78 to a resetsample output node VOUTR and through a load transistor 80 to the supplyvoltage VDD. A signal called “reset sample and hold” (SHR) briefly turnson the S/H transistor 72 immediately after the reset signal RST hascaused reset transistor 31 to turn on and reset the potential of thefloating diffusion node 30, so that the capacitor 74 stores the voltageto which the floating diffusion node 30 has been reset.

[0015] The readout circuit 60 provides correlated sampling of thepotential of the floating diffusion node 30, first of the reset chargeapplied to node 30 by reset transistor 31 and then of the stored chargefrom the photogate 24. The two samplings of the diffusion node 30charges produce respective output voltages VOUTR and VOUTS of thereadout circuit 60. These voltages are then subtracted (VOUTS-VOUTR) bysubtractor 82 to provide an output signal terminal 81 which is an imagesignal independent of pixel to pixel variations caused by fabricationvariations in the reset voltage transistor 31 which might cause pixel topixel variations in the output signal.

[0016]FIG. 2 illustrates a block diagram for a CMOS imager having apixel array 200 with each pixel cell being constructed in the mannershown by element 14 of FIG. 1. FIG. 4 shows a 2×2 portion of pixel array200. Pixel array 200 comprises a plurality of pixels arranged in apredetermined number of columns and rows. The pixels of each row inarray 200 are all turned on at the same time by a row select line, e.g.,line 86, and the pixels of each column are selectively output by acolumn select line, e.g., line 42. A plurality of rows and column linesare provided for the entire array 200. The row lines are selectivelyactivated by the row driver 210 in response to row address decoder 220and the column select lines are selectively activated by the columndriver 260 in response to column address decoder 270. Thus, a row andcolumn address is provided for each pixel. The CMOS imager is operatedby the control circuit 250 which controls address decoders 220, 270 forselecting the appropriate row and column lines for pixel readout, androw and column driver circuitry 210, 260 which apply driving voltage tothe drive transistors of the selected row and column lines.

[0017]FIG. 3 shows a simplified timing diagram for the signals used totransfer charge out of photodetector circuit 14 of the FIG. 1 CMOSimager. The photogate signal PG is nominally set to 5V and the resetsignal RST is nominally set at 2.5V. As can be seen from the figure, theprocess is begun at time t₀ by briefly pulsing reset voltage RST to 5V.The RST voltage, which is applied to the gate 32 of reset transistor 31,causes transistor 31 to turn on and the floating diffusion node 30 tocharge to the VDD voltage present at n+ region 34 (less the voltage dropVth of transistor 31). This resets the floating diffusion node 30 to apredetermined voltage (VDD−Vth). The charge on floating diffusion node30 is applied to the gate of the source follower transistor 36 tocontrol the current passing through transistor 38, which has been turnedon by a row select (ROW) signal, and load transistor 39. This current istranslated into a voltage on line 42 which is next sampled by providinga SHR signal to the S/H transistor 72 which charges capacitor 74 withthe source follower transistor output voltage on line 42 representingthe reset charge present at floating diffusion node 30. The PG signal isnext pulsed to 0 volts, causing charge to be collected in n+ region 26.A transfer gate voltage pulse TX, similar to the reset pulse RST, isthen applied to transfer gate 28 of transistor 29 to cause the charge inn+ region 26 to transfer to floating diffusion node 30. It should beunderstood that for the case of a photogate, the transfer gate voltageTX may be pulsed or held to a fixed DC potential. For the implementationof a photodiode with a transfer gate, the transfer gate voltage TX mustbe pulsed. The new output voltage on line 42 generated by sourcefollower transistor 36 current is then sampled onto capacitor 64 byenabling the sample and hold switch 62 by signal SHS. The column selectsignal is next applied to transistors 68 and 70 and the respectivecharges stored in capacitors 64 and 74 are subtracted in subtractor 82to provide a pixel output signal at terminal 81. It should also beunderstood that CMOS imagers may dispense with the transistor gate 28and associated transistor 29 or retain these structures while biasingthe transfer transistor gate 28 to an always “on” state.

[0018] The operation of the charge collection of the CMOS imager isknown in the art and is described in several publications such as Mendiset al., “Progress in CMOS Active Pixel Image Sensors,” SPIE Vol. 2172,pp. 19-29 1994; Mendis et al., “CMOS Active Pixel Image Sensors forHighly Integrated Imaging Systems,” IEEE Journal of Solid StateCircuits, Vol. 32(2), 1997; and Eric R., Fossum, “CMOS Image Sensors:Electronic Camera on a Chip, IEDM Vol. 95 pages 17-25 (1995) as well asother publications. These references are incorporated herein byreference.

[0019] Prior CMOS imagers suffer from several drawbacks regarding thecharge flow and contact between different regions of the substrate, suchas, for example the floating diffusion area 30 and the source followertransistor 36. For example, during etching to create the contact betweenthe floating diffusion region 30 and the source follower transistor 36caution must be taken to avoid over etching into the shallow n-dopedregion of die floating diffusion region so as to prevent potentialcharge leakage into the substrate during operation of the imager. Sincethe size of the pixel electrical signal is very small due to thecollection of photons in the photo array, the signal to noise ratio ofthe pixel should be as high as possible within a pixel. Thus, leakageinto the substrate is a significant problem to be avoided in CMOSimagers.

[0020] Additionally, the tungsten metal, which is typically used tocontact the different regions of the CMOS imager, is deposited withtungsten fluoride and a reaction sometimes takes place between thetungsten fluoride and the substrate resulting in the formation ofsilicon fluoride which creates worm holes in the substrate. These wormholes create a conductive channel for current to leak into thesubstrate, creating a poor performance for the imager. Also,conventional contact regions typically include a highly n-doped regionto facilitate an ohmic metal-semiconductor contact between the contactmetallization and the underlying n-doped silicon region to achievecharge transfer. However, this same highly doped n+ region 30 createscurrent leakage into the substrate due to high electric fields caused bythe abrupt junction. Also, typically there must be an over etch of thecontact to account for non-uniformities across the wafer andnon-uniformity of the BPSG thickness.

[0021] Examples of the above-described drawbacks can be seen from FIGS.5-7 which show a side view of several CMOS imagers of the prior art anddescribe the floating diffusion and source follower transistor gatecontact. It should be understood that these drawbacks are also presentwhere a metal contact is required to electrically connect the CMOSimagers of the prior art. It should be understood that similar referencenumbers correspond to similar elements for FIGS. 5-7.

[0022] Reference is now made to FIG. 5. This figure shows the regionbetween the floating diffusion and the source follower transistor of aprior CMOS imager having a photogate as the photoactive area and furtherincludes a transfer gate. The imager 100 is provided with three dopedregions 143, 126 and 115, which are doped to a conductivity typedifferent from that of the substrate, for exemplary purposes regions143, 126 and 115 are treated as n type, which are within a p-well of asubstrate. The first doped region 143 is the photosite charge collector,and it underlies a portion of the photogate 142, which is a thin layerof material transparent or partially transparent to radiant energy, suchas polysilicon. The first doped region 143 is typically an n-dopedregion. An insulating layer 140 of silicon dioxide, silicon nitride, orother suitable material is formed over a surface of the doped layer 143of the substrate between the photogate 142 and first doped region 143.

[0023] The second doped region 126 transfers charge collected by thephotogate 142 and it serves as the source for the transfer transistor128. The transfer transistor 128 includes a transfer gate 139 formedover a gate oxide layer 140. The transfer gate 139 has insulatingspacers 149 formed on its sides.

[0024] The third doped region 115 is the floating diffusion region andis connected to a gate 136 of a source follower transistor by contactlines 125, 127, 129 which are typically metal contact lines as describedin more detail below. The imager 100 typically includes a highly n+doped region 120 within n-doped region 115 under the floating diffusionregion contact 125 which provides good ohmic contact of the contact 125with the n-doped region 115. The floating diffusion contact 125 connectsn+ region 120 of the floating diffusion region with the gate 136 of thesource follower transistor. In other embodiments of the prior art, theentire region 115 may be doped n+ thereby eliminating the need for n+region 120.

[0025] The source and drain regions of the source follower transistorare not seen in FIG. 5 as they are perpendicular to the page but are oneither side of gate 136. The source follower gate 136 is usually formedof a doped polysilicon which may be silicided and which is depositedover a gate oxide 140, such as silicon dioxide. The floating diffusioncontact 125 is usually formed of a tungsten plug typically a Ti/TiN/Wmetallization stack as described in further detail below. The floatingdiffusion contact 125 is formed in an insulating layer 135 which istypically an undoped oxide followed by the deposition of a doped oxidesuch as a BPSG layer deposited over the substrate. The tungsten metalwhich forms the floating diffusion/source follower contact 125 istypically deposited using a tungsten fluoride such as WF₆.

[0026] Typically, the layer 135 must be etched with a selective dry etchprocess prior to depositing the tungsten plug connector 125. The imager100 also includes a source follower contact 127 formed in layer 135 in asimilar fashion to floating diffusion contact 125. Source followercontact 127 is also usually formed of a tungsten plug typically aTi/TiN/W metallization stack as described in further detail below. Thefloating diffusion contact 125 and the source follower contact 127 areconnected by a metal layer 129 formed over layer 135. Typically metallayer 129 is formed of aluminum, copper or any other metal.

[0027] Separating the source follower transistor gate 136 and thefloating diffusion region 115 is a field oxide layer 132, which servesto surround and isolate the cells. The field oxide 132 may be formed bythermal oxidation of the substrate or in the Local Oxidation of Silicon(LOCOS) or by the Shallow Trench Isolation (STI) process which involvesthe chemical vapor deposition of an oxide material.

[0028] It should be understood that while FIG. 5 shows an imager havinga photogate as the photoactive area and additionally includes a transfertransistor, additional imager structures are also well known. Forexample, CMOS imagers having a photodiode or a photoconductor as thephotoactive area are known. Additionally, while a transfer transistorhas some advantages as described above, it is not required.

[0029] The prior art metal contacts 125, 127 described with reference toFIG. 5 typically include a thin layer 123 formed of titanium, titaniumnitride or a mixture thereof formed in the etched space in the layer135. A tungsten plug 122 is then filled in the etched space in the layer135 inside the thin layer 123. The contact 125 contacts n+ region 120and forms a TiSi₂ area 121 by a reaction between the titanium from layer123 with the silicon substrate in n+ region 120.

[0030] Reference is now made to FIG. 6. This figure illustrates apartially cut away side view of a semiconductor imager undergoing aprocessing method according to the prior art. The imager 104 has thefloating diffusion region 115 having an n+ doped region 120 and thesource follower transistor gate 136 already formed therein. The floatingdiffusion 115 and the source follower gate 136 are under layer 135,which, as noted, is preferably composed of oxides, typically a layeredstructure of an undoped and doped, i.e., BPSG, oxides. A resist 155 isapplied to layer 135 in order to etch through layer 135 to form thecontacts to the floating diffusion region 115 and the source followertransistor gate 136. Layer 135 is then etched to form the hole 156 inlayer 135 for the floating diffusion contact 125 and hole 157 in layer135 for the source follower transistor contact 127 as shown in FIG. 7.However, as can be seen from FIG. 7, since the field oxide 132 and layer135 are both similar oxides it is difficult to control the etchingprocess when attempting to align the hole 156 with the edge of the fieldoxide 132. In fact, the etching process often etches deep into the n+region 120 or etches through the exposed edge of the field oxide 132causing charge leakage to the substrate as shown by the arrows in FIG.7. Etching deep into the n+ region 120 results in poor contactresistance to the n+ region 120. Etching through the n+ region 120 orthrough the exposed region of the filed oxide 132 can result in chargeleakage to the substrate.

[0031] The devices described with reference to FIGS. 5-7 have severaldrawbacks. For example, during etching, caution must be taken to avoidetching through the n+ layer 120 or even deep into n-doped region 115where the n-type dopant concentration is reduced. Additionally, when thetungsten metal is deposited by the tungsten fluoride, a reactionsometimes takes place between the tungsten fluoride and the substrateresulting in the formation of silicon fluoride which creates worm holesthrough the n+ region 120 and into the substrate. These worm holes maycreate a channel for current to leak into the substrate, creating a poorperformance for the imager. While Ti/TiN barrier layers are deposited toform a good ohmic contact to the n+ region due to the TiSi2 reaction andprovide a TiN barrier between the W metallization and the Si substrate,worm holes and contact leakage still occur. Also, the prior art floatingdiffusion region 115 included the highly n+ region 120 to provide anohmic contact; however, this same highly doped n+ region sets up highelectric fields with respect to the p-type region under field oxideregion 132 which fosters current leakage into the substrate.Accordingly, a better contact which provides a good ohmic contact, whileavoiding substrate leakage is needed.

SUMMARY OF THE INVENTION

[0032] The present invention provides a CMOS imager having aself-aligned contact. In a preferred implementation, the self-alignedcontact is between the floating diffusion region and the gate of thesource follower transistor. The self-aligned contact provides a betterohmic contact with less chance leakage into the substrate. Theself-aligned contact allows the electrical connection of the devicewithout the possibility of etching into the substrate, and therebycausing leakage, while providing a sufficient ohmic contact. Theself-aligned contact also allows the imager components to be placedcloser together, thereby reducing size of a pixel and allowing anincreased photoarea per cell size which, it turn, increases the signalto noise ratio of the imager. In addition, the problems with worm holesand connecting of the floating diffusion contact are completely avoidedas there is no need for the highly doped n+ region 120 in the presentinvention and additionally no need for any metallization to be directlyin contact with the silicon substrate.

[0033] The above and other advantages and features of the invention willbe more clearly understood from the following detailed description whichis provided in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0034]FIG. 1 is a representative circuit of a CMOS imager.

[0035]FIG. 2 is a block diagram of a CMOS active pixel sensor chip.

[0036]FIG. 3 is a representative timing diagram for the CMOS imager.

[0037]FIG. 4 is a representative pixel layout showing a 2×2 pixel layoutaccording to one embodiment of the present invention.

[0038]FIG. 5 is a partially cut away side view of a semiconductor imagerhaving a photogate and a transfer gate according to the prior art.

[0039]FIG. 6 shows a partially cut away side view of a semiconductorimager undergoing a processing method according to the prior art.

[0040]FIG. 7 shows a partially cut away side view of a semiconductorimager undergoing a processing method according to the prior artsubsequent to FIG. 6.

[0041]FIG. 8 shows a partially cut away side view of a semiconductorimager of a first embodiment of the present invention at an intermediatestep of processing.

[0042]FIG. 9 shows a partially cut away side view of a semiconductorimager of the present invention subsequent to FIG. 8.

[0043]FIG. 10 shows a partially cut away side view of a semiconductorimager of the present invention subsequent to FIG. 9.

[0044]FIG. 11 shows a partially cut away side view of a semiconductorimager of the present invention subsequent to FIG. 10.

[0045]FIG. 12 shows a partially cut away side view of a semiconductorimager of the present invention subsequent to FIG. 11.

[0046]FIG. 13 shows a partially cut away side view of a semiconductorimager of another embodiment at an intermediate step of processing.

[0047]FIG. 14 shows a partially cut away side view of a semiconductorimager of the present invention subsequent to FIG. 13.

[0048]FIG. 15 shows a partially cut away side view of a semiconductorimager of the present invention subsequent to FIG. 14.

[0049]FIG. 16 is an illustration of a computer system having a CMOSimager according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0050] In the following detailed description, reference is made to theaccompanying drawings which form a part hereof, and in which is shown byway of illustration specific embodiments in which the invention may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice the invention, and it is tobe understood that other embodiments may be utilized, and thatstructural, logical and electrical changes may be made without departingfrom the spirit and scope of the present invention.

[0051] The terms “wafer” and “substrate” are to be understood asincluding silicon-on-insulator (SOI) or silicon-on-sapphire (SOS)technology, doped and undoped semiconductors, epitaxial layers ofsilicon supported by a base semiconductor foundation, and othersemiconductor structures. Furthermore, when reference is made to a“wafer” or “substrate” in the following description, previous processsteps may have been utilized to form regions or junctions in the basesemiconductor structure or foundation. In addition, the semiconductorneed not be silicon-based, but could be based on silicon-germanium,germanium, or gallium arsenide.

[0052] The term “pixel” refers to a picture element unit cell containinga photosensor and transistors for converting electromagnetic radiationto an electrical signal. For purposes of illustration, a representativepixel is illustrated in the figures and description herein, andtypically fabrication of all pixels in an imager will proceedsimultaneously in a similar fashion. The following detailed descriptionis, therefore, not to be taken in a limiting sense, and the scope of thepresent invention is defined by the appended claims.

[0053] The invention is now described with reference to FIGS. 8-15. FIG.8 shows a partially cut away cross-sectional view of a CMOSsemiconductor wafer similar to that shown in FIG. 1. It should beunderstood that similar reference numbers correspond to similar elementsfor FIGS. 8-15. FIG. 8 shows the region between the floating diffusionand the source follower transistor for an imager having a photodiode asthe photosensitive area and which includes a transfer gate 328. As withFIG. 5 above, the source follower transistor source and drain regionsare in a plane perpendicular to FIG. 8.

[0054] The pixel cell 300 includes a substrate which includes a p-typewell 311 formed in a substrate. It should be understood that the CMOSimager of the present invention can also be fabricated using p-dopedregions in an n-well. The pixel cell 300 also includes a field oxideregion 332, which serves to surround and isolate the cells. The fieldoxide region 332 may be formed by thermal oxidation of the substrateusing the LOCOS process or by the STI process which involves thechemical vapor deposition of an oxide material.

[0055] The pixel cell 300 includes an oxide or other insulating film 318deposited on the substrate by conventional methods. Preferably the oxidefilm 318 is formed of a silicon dioxide grown onto the substrate.

[0056] A transfer transistor 328 is formed by depositing a conductivegate layer 339 and an insulating layer 340 over the insulating layer 318as shown in FIG. 8. A source follower transistor gate 320, and a resettransistor gate 326 are also formed over the insulating layer 318 atthis stage of processing. The gate layers 339 of the transistors arepreferably formed of doped polysilicon formed by physical depositionmethods such as chemical vapor deposition (CVD) or physical vapordeposition. The gate layers 339 may also be formed of a compositelayered structure of doped polysilicon/refractory metal silicide orbarrier metal, if desired, according to conventional methods. Preferablythe refractory metal silicide is a tungsten, titanium, tantalum orcobalt silicide. The barrier metal may be those such as titaniumnitride, tungsten nitride or the like.

[0057] The insulating layer 340 formed on the gates of each of thetransfer, reset and source follower transistors may be a nitride, anoxide or a combination thereof, such as, for example, anoxide/nitride/oxide (ONO) layer, an oxide/nitride (ON) layer or anitride/oxide layer (NO). Most preferably the insulating layer 340 is anON layer. The insulating layers 340 may be formed by CVD.

[0058] The transfer gate 328, the source follower gate 320, and thereset gate 326 have sidewall insulating spacers 349 formed on the sidesof the transistor gates 339, 320, 326 as shown in FIG. 9. The spacersmay be formed out of oxide or nitride or oxynitride. An n-doped region315 is formed in p-well 311 by ion implantation and n-doped region 352is also formed in p-well 311 by ion implantation in the area that willlater become the photodiode 350 as shown in FIG. 9.

[0059] N-doped region 354 is also provided in p-well 311 in the areathat will later become the reset drain for the CMOS imager. It should beunderstood that the regions 315, 352 and 354 may be doped to the same ordiffering dopant concentration levels. Additionally, while two separatedoped regions are shown in the figure, a single doped region could beformed to incorporate both regions 315 and 352 if the transfertransistor is omitted. There may be other dopant implantations appliedto the wafer at this stage of processing such as n-well and p-wellimplants or transistor voltage adjusting implants. For simplicity, theseother implants are not shown in the figure.

[0060] Reference is now made to FIG. 10. A layer 360 ofborophosphorosilicate glass (BPSG), phososilicate glass (PSG),borosilicate glass (BSG), undoped SiO₂ or the like is deposited over thesubstrate and preferably planarized by CMP or other methods. A resistand mask (not shown) is applied to the layer 360 and the resist isdeveloped and the layer 360 is etched to create the opening 357. Thelayer 360 may be etched by any conventional methods such as a selectivewet etch or a selective dry etch to form opening 357. The dry etchconditions and the insulating cap composition and the spacer compositionare selected so that the dry or wet etch will etch the layer 360 but notthe insulating cap 340 or the spacer 349. A selective etch to etch BPSGlayer 360 and not etch nitride spacers 349 would typically be conductedby photomasking and dry chemical etching of BPSG selective to thenitride. An example etch chemistry would include CHF₃ and O₂ at low O₂flow rate (i.e., less than 5% O₂ by volume in a CHF3/O₂ mixture), or thecombination of CF₄, CH₂F₂ and CHF₃. See, for example, U.S. Pat. No.5,338,700 which is herein incorporated by reference.

[0061] In order to etch BPSG layer 360 and not the other oxides, forexample field oxide layer 332, the selective etching process isperformed by photomasking and dry chemical etching of BPSG selective tothe oxide. An example etch chemistry would include C₂HF₅, CHF₃ andCH₂F₂. Preferably, the oxide selective etch is performed in a LAM 9100etching apparatus at a C₂HF₅, CHF₃ and CH₂F₂ ratio of 1:3:4.

[0062] Polysilicon is then deposited by conventional methods to fillopening 357. The polysilicon is then etched back or planarized by CMP orother methods to form the self-aligned buried contact 325 in the opening357 as shown in FIG. 11.

[0063] Reference is now made to FIG. 12. A layer 361 ofborophosphorosilicate glass (BPSG), phososilicate glass (PSG),borosilicate glass (BSG), undoped SiO₂ or the like is then deposited andplanarized by CMP or other methods. A resist and mask (not shown) arethen applied and the layer 361 is etched to form interconnects 370 and371 over the n-type polysilicon plug 325 and the source followertransistor gate 320 respectively. The layer 361 may be etched by anyconventional methods such as a selective wet etch or a selective dryetch. Interconnects 370 and 371 are the same or different and may beformed of any typical interconnect conductive material such as metals ordoped polysilicon. Interconnects 370 and 371 may be formed of dopedpolysilicon, refractory metals, such as, for example, tungsten ortitanium or any other materials, such as a composite Ti/TiN/Wmetallization stack as is known in the art. Since the interconnect 370connects to the self-aligned buried contact 357 through the n-typepolysilicon plug 325, as opposed to floating diffusion region 315itself, there is less concern about overetching the layer 361 to formthe hole for interconnect 370 as no leakage to the substrate will resultfrom overetching the contact hole for interconnect 370. Theinterconnects 370 and 371 are connected by interconnect 375 which isformed over layer 361. Interconnect 375 may also be formed of any dopedpolysilicon, refractory or non-refractory metals, such as, for example,tungsten or Al or Al—Cu or Cu or any other materials, such as acomposite Ti/TiN/W metallization stack as is known in the art.Interconnect 375 may be formed of the same or different material asinterconnects 370, 371 and may be formed at the same or different timesas interconnects 370, 371.

[0064] After the processing to produce the imager shown in FIG. 12, thepixel cell 301 of the present invention is then processed according toknown methods to produce an operative imaging device. The self-alignedburied contact 325 is considered buried because of additional materiallayers which are formed over the substrate to produce an operative CMOSimager circuit. For example, an insulating layer 361 may be applied andplanarized and contact holes etched therein as shown in to formconductor paths to transistor gates, etc. Conventional metal andinsulation layers are formed over layer 361 and in the through holes tointerconnect various parts of the circuitry in a manner similar to thatused in the prior art to form gate connections. Additional insulatingand passivation layers may also be applied. The imager is fabricated toarrive at an operational apparatus that functions similar to the imagerdepicted in FIGS. 1-4. The self-aligned buried contact 325 is buriedwell below the normal metal layers which are applied over layer 361 andwhich are used to interconnect the IC circuitry to produce a CMOSimager.

[0065] The self-aligned buried contact 325 between the floatingdiffusion region 315 and the source follower transistor gate 320 viainterconnection lines 370, 375, 371 provides a good contact between thefloating diffusion region 315 and the source follower transistor gate320 without using processing techniques which might cause charge leakageto the substrate during device operation. The self-aligned buriedcontact 325 also allows the transfer and reset transistors to be placedcloser together adjacent to the floating diffusion region 315 therebyallowing for an increased photosensitive area on the pixel and a reducedfloating diffusion region which reduces the leakage of charge tosubstrate when the floating diffusion is charged and which increases thesignal to noise ratio of the imager.

[0066] Reference is now made to FIGS. 13-15. FIG. 13 illustrates apartially cut away side view of a semiconductor imager undergoing aprocessing method according to the present invention. This figure showsa partially cut away semiconductor imager similar to that shown in FIGS.8-12. The imager as illustrated in FIGS. 13-15 is fabricated in asimilar fashion to that described above with reference to FIGS. 8-12. Itshould be understood that like reference numerals designate likeelements.

[0067] The pixel cell 301 includes a substrate which includes a p-typewell 311 formed in a substrate. The pixel cell 301 includes an n-dopedregion 315 which forms the floating diffusion region. It should beunderstood that the CMOS imager of the present invention can also befabricated using p-doped regions in an n-well.

[0068] The pixel cell 301 also includes a field oxide region 332, whichserves to surround and isolate the cells which may be formed by thermaloxidation of the substrate using the LOCOS process or by the STI processwhich involve the chemical vapor deposition of an oxide material. Thefield oxide region 332 forms an isolation region around the sourcefollower transistor area 330.

[0069] The pixel cell 301 includes an oxide or other insulating film 318deposited on the substrate by conventional methods. Preferably the oxidefilm 318 is formed of a silicon dioxide grown onto the substrate. Atransfer transistor 328 is formed by depositing a gate conductor layer339 and a protective insulating layer 359 over the insulating layer 318and patterning and etching the gate conductor/gate insulator layerssimultaneously as shown in FIG. 13. A source follower transistor gate320 is similarly formed over the insulating layer 318 at this stage ofprocessing. The gate conductor 339 is formed of doped polysilicon formedby physical deposition methods such as chemical vapor deposition (CVD)or physical vapor deposition. The gate conductor 339 may also be formedof a composite layered structure of doped polysilicon/barrier/metal forimproved conductivity, if desired, according to conventional methods.Preferably the refractory metal silicide is a tungsten, titanium orcobalt silicide. The barrier can be, for example, titanium nitride ortungsten nitride. The metal can be, for example, a refractory metal suchas tungsten. Preferably the protective layer 359 is a nitride or anoxide or a combination thereof, such as an oxide/nitride/oxide (ONO)layer, an oxide/nitride (ON) layer or a nitride/oxide layer (NO). Mostpreferably the protective layer 359 is an ONO layer. The protectivelayer may be formed over the gate conductive layer 339 by CVD. Thetransfer transistor 328 and the source follower transistor 320 havesidewall insulating spacers 349 as shown in FIG. 13. The sidewallspacers 349 may be formed out of oxide, nitride or oxynitride.

[0070] An n-doped region 315 is provided in p-well 311 as shown in FIG.13. A doped region 352 is also formed in the substrate as shown in FIG.13 in the area that will later become the photodiode 350. It should beunderstood that the regions 315 and 352 may be doped to the same ordifferent dopant concentration levels. Additionally, while two separatedoped regions are shown in the figure, a single doped region could beformed to incorporate both regions 315 and 352. There may be otherdopant implantations applied to the wafer at this stage of processingsuch as n-well and p-well implants or transistor voltage adjustingimplants. For simplicity, these other implants are not shown in thefigure.

[0071] Reference is made to FIG. 14. A layer 360 ofborophosphorosilicate glass (BPSG), phososilicate glass (PSG),borosilicate glass (BSG), undoped SiO₂ or the like is deposited over thesubstrate p-well 311. A resist and mask (not shown) is applied to thelayer 360 and the resist is developed and the layer 360 is etched tocreate the opening 357. The layer 360 may be etched by a selective wetetch or a selective dry etch to form opening 357. A selective etch toetch BPSG layer 360 and not etch nitride spacers 349 or protective layer359 would typically be conducted by photomasking and dry chemicaletching of BPSG selective to the nitride. An example etch chemistrywould include CHF₃ and O2 at low O₂ flow rate (i.e., less than 5% O₂ byvolume in a CHF3/O2 mixture), or the combination of CF4, CH2F2 and CHF3.See, U.S. Pat. No. 5,338,700 which is herein incorporated by reference.

[0072] In order to etch BPSG layer 360 and not the other oxides, forexample field oxide layer 332, the selective etching process isperformed by photomasking and dry chemical etching of BPSG selective tothe oxide. An example etch chemistry would include C₂HF₅, CHF₃ andCH₂F₂. Preferably, the oxide selective etch is perfumed in a LAM 9100etching apparatus at a C₂HF₅, CHF₃ and CH₂F₂ ratio of 1:3:4.

[0073] The self-aligned buried contact 325 is then formed in the opening357 in the layer 360. The self-aligned buried contact 325 may be formedby conventional methods. Preferably the self-aligned buried contact 325is formed by chemical vapor deposition of doped polysilicon with afollowing polysilicon dry or wet etchback or a polysilicon CMP to leavethe polysilicon only in the opening 357.

[0074] Reference is now made to FIG. 15. The layer 362 is then depositedand planarized by CMP or other methods. A resist (not shown) is thenapplied, openings are patterned using photolithography, and the layers360, 362, and 359 are etched to form interconnects 370 and 371 over theself-aligned buried contact 325 and the source follower transistor gate320 respectively. The layers 359, 360, 362 may be etched by anyconventional methods such as a selective wet etch or a selective dryetch. Interconnects 370 and 371 may be formed, the same or differently,of any typical interconnect conductive material such as metals or dopedpolysilicon. Interconnects 370 and 371 may be formed of dopedpolysilicon, refractory metals, such as, for example, tungsten ortitanium or any other materials, such as a composite Ti/TiN/Wmetallization stack as is known in the art. Since the interconnect 370connects to the self-aligned buried contact 325, as opposed to floatingdiffusion region 315 itself, there is less concern about overetching thelayers 360 and 362 to form the hole for interconnect 370 as no leakageto the substrate will result from overetching the contact hole forinterconnect 370. The interconnects 370 and 371 are connected byinterconnect 375 which is formed over layer 362. Interconnect 375 mayalso be formed of any doped polysilicon, refractory metals, such as, forexample, tungsten, copper, aluminum, an aluminum-copper alloy or anyother materials, such as a composite Ti/TiN/W metallization stack as isknown in the art. Interconnect 375 may be formed of the same ordifferent material as interconnects 370, 371 and may be formed at thesame or different times as interconnects 370, 371.

[0075] After the processing to produce the imager shown in FIG. 15, thepixel cell 301 of the present invention is then processed according toknown methods to produce an operative imaging device. The self-alignedburied contact 325 is considered buried because of additional materiallayers which are formed over the substrate to produce an operative CMOSimager circuit. For example, an insulating layer 362 may be applied andplanarized and contact holes etched therein as shown in to formconductor paths to transistor gates, etc. Conventional metal andinsulation layers are formed over layer 362 to interconnect variousparts of the circuitry in a manner similar to that used in the prior artto form gate connections. Additional insulating and passivation layersmay also be applied. The imager is fabricated to arrive at anoperational apparatus that functions similar to the imager depicted inFIGS. 1-4. The self-aligned buried contact 325 is buried well below thenormal metal layers which are applied over layer 362 and which are usedto interconnect the IC circuitry to produce a CMOS imager.

[0076] The self-aligned buried contact 325 between the floatingdiffusion region 315 and the source follower transistor gate 320 viainterconnection lines 370, 375, 371 provides a good contact between thefloating diffusion region 315 and the source follower transistor gate320 without using processing techniques which might cause charge leakageto the substrate during device operation. The self-aligned buriedcontact 325 also allows the source follower transistor to be placedcloser to the floating diffusion region 315 thereby allowing for anincreased photosensitive area on the pixel and a short conductor lengthbetween the floating diffusion region and gate of the source followertransistor which increases the signal to noise ratio of the imager.

[0077] The pixel arrays of the present invention described withreference to FIGS. 8-15 may be further processed as known in the art toarrive at CMOS imagers representative of those discussed above withreference to FIGS. 1-4 and having the buried conductor of the presentinvention.

[0078] A typical processor based system which includes a CMOS imagerdevice according to the present invention is illustrated generally at500 in FIG. 16. A processor based system is exemplary of a system havingdigital circuits which could include CMOS imager devices. Without beinglimiting, such a system could include a computer system, camera system,scanner, machine vision, vehicle navigation, video phone, surveillancesystem, auto focus system, star tracker system, motion detection system,image stabilization system and data compression system forhigh-definition television, all of which can utilize the presentinvention.

[0079] A processor based system, such as a computer system, for examplegenerally comprises a central processing unit (CPU) 544, for example, amicroprocessor, that communicates with an input/output (I/O) device 546over a bus 552. The CMOS imager 542 also communicates with the systemover bus 452. The computer system 500 also includes random access memory(RAM) 548, and, in the case of a computer system may include peripheraldevices such as a floppy disk drive 554 and a compact disk (CD) ROMdrive 556 which also communicate with CPU 544 over the bus 552. CMOSimager 542 is preferably constructed as an integrated circuit whichincludes the CMOS imager having a buried contact line between thefloating diffusion region and the source follower transistor, aspreviously described with respect to FIGS. 8-17. It may also bedesirable to integrate the processor 554, CMOS imager 542 and memory 548on a single IC chip.

[0080] It should again be noted that although the invention has beendescribed with specific reference to CMOS imaging circuits having aphotogate and a floating diffusion, the invention has broaderapplicability and may be used in any CMOS imaging apparatus. Forexample, the CMOS imager array can be formed on a single chip togetherwith the logic or the logic and array may be formed on separate ICchips. Additionally, while the figures describe the invention withrespect to a photodiode type of CMOS imager, any type of photocollectiondevices such as photogates, photoconductors or the like may find use inthe present invention. Similarly, the process described above is but onemethod of many that could be used. Additionally, although the inventionis described with respect to forming the self-aligned buried contact 325between a transfer gate 328 and a reset gate 326, it should beunderstood that the self-aligned buried contact 325 may be formedbetween any two transistor gates. Accordingly, the above description andaccompanying drawings are only illustrative of preferred embodimentswhich can achieve the features and advantages of the present invention.It is not intended that the invention be limited to the embodimentsshown and described in detail herein. The invention is only limited bythe scope of the following claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. An imaging device comprising: a substrate; aphotosensitive area within said substrate for accumulatingphoto-generated charge in said area; a floating diffusion region in saidsubstrate for receiving charge from said photosensitive area; a readoutcircuit comprising at least an output transistor formed in saidsubstrate; and, a self-aligned buried contact for interconnecting saidfloating diffusion region with said output transistor.
 2. The imagingdevice according to claim 1, wherein the accumulation of charge in saidphotosensitive area is conducted by a photoconductor.
 3. The imagingdevice according to claim 1, wherein the accumulation of charge in saidphotosensitive area is controlled by a photogate.
 4. The imaging deviceaccording to claim 1, wherein said photosensitive area is a photodiode.5. The imaging device according to claim 1, further including a chargetransfer region between said photosensitive area and said floatingdiffusion region, said charge transfer region including a field effecttransistor, wherein said self-aligned buried contact is aligned to agate structure of said field effect transistor.
 6. The imaging deviceaccording to claim 5, wherein said output transistor is a sourcefollower transistor and wherein said self-aligned buried contactconnects said floating diffusion region and said source followertransistor via interconnectors.
 7. The imaging device according to claim6, wherein said interconnectors are formed at least in part of dopedpolysilicon.
 8. The imaging device according to claim 6, wherein saidinterconnectors are formed of at least one refractory metal.
 9. Theimaging device according to claim 8, wherein said refractory metal istungsten.
 10. The imaging device according to claim 6, wherein saidinterconnectors are formed of aluminum-copper alloy.
 11. The imagingdevice according to claim 6, wherein said interconnectors are formed ofcopper.
 12. The imaging device according to claim 8, wherein saidrefractory metal is titanium.
 13. The imaging device according to claim6 wherein the accumulation of charge in said photosensitive area isconducted by a photoconductor.
 14. The imaging device according to claim6, wherein the accumulation of charge in said photosensitive area isconducted by a photogate.
 15. The imaging device according to claim 6,wherein said photosensitive area is a photodiode.
 16. The imaging deviceaccording to claim 5, further comprising an insulating layer formed overthe gate of said transfer transistor and said source follower transistorand under the self-aligned buried contact.
 17. The imaging deviceaccording to claim 16, wherein said insulating layer includes a nitride.18. The imaging device according to claim 16, wherein said insulatinglayer includes an oxide.
 19. The imaging device according to claim 17,wherein said insulating layer is selected from a nitride, ONO, NO, ON orcombinations thereof.
 20. An imaging device comprising: a substratehaving a photosensitive area therein for accumulating photo-generatedcharge in said area; a region in said substrate for receiving chargefrom said photosensitive area; a device for controlling said charge,said device including a conductive layer, an insulating layer over saidconductive layer and an insulating spacer adjacent said conductivelayer; and, a buried contact adjacent said insulating spacer forinterconnecting said region with said device.
 21. The imaging deviceaccording to claim 20, wherein the accumulation of charge in saidphotosensitive area is conducted by a photoconductor.
 22. The imagingdevice according to claim 20, wherein the accumulation of charge in saidphotosensitive area is controlled by a photogate.
 23. The imaging deviceaccording to claim 20, wherein said photosensitive area is a photodiode.24. The imaging device according to claim 20, wherein said insulatinglayer is selected from the group consisting of a nitride, an oxide, ON,NO, ONO and an antireflective layer.
 25. The imaging device according toclaim 20, wherein said insulating spacer is selected from the groupconsisting of a nitride, an oxide, ON, NO and ONO.
 26. The imagingdevice according to claim 20, wherein said conductive layer is selectedfrom doped polysilicon, refractory metal silicides, barrier metals orcombinations thereof.
 27. The imaging device according to claim 26,wherein said conductive layer includes tungsten silicide, titaniumsilicide, cobalt silicide and mixtures thereof formed over a dopedpolysilicon layer.
 28. The imaging device according to claim 26, whereinsaid conductive layer includes tungsten, titanium, tungsten nitride,titanium nitride and mixtures thereof.
 29. An imaging device comprisinga semiconductor integrated circuit substrate; a photosensitive deviceformed on said substrate for accumulating photo-generated charge in anunderlying region of said substrate; a floating diffusion region in saidsubstrate for receiving said photo-generated charge; a readout circuitcomprising at least an output transistor formed in said substrate; andsaid floating diffusion region being connected to said output by aself-aligned buried contact via interconnectors.
 30. The imaging deviceaccording to claim 29, wherein said photosensitive device is aphotogate.
 31. The imaging device according to claim 29, wherein saidphotosensitive device is a photodiode.
 32. The imaging device accordingto claim 29, wherein said photosensitive device is a photoconductor. 33.The imaging device according to claim 29, further including a chargetransfer region between said photosensitive area and said floatingdiffusion region, said charge transfer region including a field effecttransistor, wherein said self-aligned buried contact is aligned to saidfield effect transistor.
 34. The imaging device according to claim 33,wherein said output transistor is a source follower transistor andwherein said self-aligned buried contacts said floating diffusion regionand said source follower transistor via interconnectors.
 35. The imagingdevice according to claim 34, wherein said interconnectors are formed atleast in part of doped polysilicon.
 36. The imaging device according toclaim 34, wherein said interconnectors are formed of at least onerefractory metal.
 37. The imaging device according to claim 34, whereinsaid interconnectors are formed of aluminum-copper alloy.
 38. Theimaging device according to claim 34, wherein said interconnectors areformed of copper.
 39. The imaging device according to claim 36, whereinsaid refractory metal is tungsten.
 40. The imaging device according toclaim 36, wherein said refractory metal is titanium.
 41. The imagingdevice according to claim 33, wherein the accumulation of charge in saidphotosensitive area is conducted by a photoconductor.
 42. The imagingdevice according to claim 33, wherein the accumulation of charge in saidphotosensitive area is conducted by a photogate.
 43. The imaging deviceaccording to claim 33, wherein said photosensitive area is a photodiode.44. The imaging device according to claim 29, wherein said outputtransistor is formed adjacent to said floating diffusion region on saidsubstrate.
 45. The imaging device according to claim 29, furthercomprising a reset transistor for resetting said floating diffusionregion to a predetermined voltage.
 46. The imaging device according toclaim 29, wherein said floating diffusion region is an n-doped region ina p-well.
 47. The imaging device according to claim 42, wherein saidphotogate is formed of doped polysilicon.
 48. The imaging deviceaccording to claim 43, further comprising a lightly n-doped regionbeneath said photodiode.
 49. The imaging device according to claim 30,further comprising an insulating layer formed over the gate of saidtransfer transistor and said source follower transistor and under theself-aligned buried contact.
 50. The imaging device according to claim49, wherein said insulating layer includes a nitride.
 51. The imagingdevice according to claim 49, wherein said insulating layer includes anoxide.
 52. The imaging device according to claim 50, wherein saidinsulating layer is selected from a nitride, ONO, NO, ON or combinationsthereof.
 53. A processing system comprising: (i) a processor; and (ii) aCMOS imaging device coupled to said processor and including: asubstrate; a photosensitive area within said substrate for accumulatingphoto-generated charge in said area; a floating diffusion region in saidsubstrate for receiving charge from said photosensitive area; a readoutcircuit comprising at least an output transistor formed in saidsubstrate; and, a self-aligned buried contact for interconnecting saidfloating diffusion region with said output transistor.
 54. The systemaccording to claim 53, wherein the accumulation of charge in saidphotosensitive area is conducted by a photoconductor.
 55. The systemaccording to claim 53, wherein the accumulation of charge in saidphotosensitive area is controlled by a photogate.
 56. The systemaccording to claim 53, wherein said photosensitive area is a photodiode.57. The system according to claim 53, further including a chargetransfer region between said photosensitive area and said floatingdiffusion region, said charge transfer region including a field effecttransistor, wherein said self-aligned buried contact is aligned to saidfield effect transistor.
 58. The system according to claim 57, whereinsaid output transistor is a source follower transistor and wherein saidself-aligned buried contacts said floating diffusion region and saidsource follower transistor via interconnectors.
 59. The system accordingto claim 58, wherein said interconnectors are formed at least in part ofdoped polysilicon.
 60. The system according to claim 58, wherein saidinterconnectors are formed of at least one refractory metal.
 61. Thesystem according to claim 58, wherein said interconnectors are formed ofaluminum copper alloy.
 62. The system according to claim 58, whereinsaid interconnectors are formed of copper.
 63. The system according toclaim 60, wherein said refractory metal is tungsten.
 64. The systemaccording to claim 60, wherein said refractory metal is titanium. 65.The system according to claim 57, wherein the accumulation of charge insaid photosensitive area is conducted by a photoconductor.
 66. Thesystem according to claim 57, wherein the accumulation of charge in saidphotosensitive area is conducted by a photogate.
 67. The systemaccording to claim 57, wherein said photosensitive area is a photodiode.68. The system according to claim 57, further comprising an insulatinglayer formed over the gate of said transfer transistor and said sourcefollower transistor and under the self-aligned buried contact.
 69. Thesystem according to claim 68, wherein said insulating layer includes anitride.
 70. The system according to claim 68, wherein said insulatinglayer includes an oxide.
 71. The system according to claim 69, whereinsaid insulating layer is selected from a nitride, ONO, NO, ON orcombinations thereof.
 72. An imaging device comprising: a substrate; aphotosensitive area within said substrate for accumulatingphoto-generated charge in said area; a readout circuit comprising atleast an output transistor formed in said substrate; and, a self-alignedburied contact formed over a doped region in said substrate and betweentwo structures on said substrate for electrically connecting saidimaging device, wherein said structures are selected from a transistorgate and an isolation region.
 73. The imaging device according to claim72, wherein the accumulation of charge in said photosensitive area isconducted by a photoconductor.
 74. The imaging device according to claim72, wherein the accumulation of charge in said photosensitive area iscontrolled by a photogate.
 75. The imaging device according to claim 72,wherein said photosensitive area is a photodiode.
 76. The imaging deviceaccording to claim 72, further including a charge transfer transistorand a reset transistor, wherein said self-aligned buried contact isaligned between said transfer transistor and said reset transistor. 77.The imaging device according to claim 76, wherein said self-alignedburied contacts electrically connects said imaging device viainterconnectors.
 78. The imaging device according to claim 77, whereinsaid interconnectors are formed at least in part of doped polysilicon.79. The imaging device according to claim 77, wherein saidinterconnectors are formed of at least one refractory metal.
 80. Theimaging device according to claim 77, wherein said interconnectors areformed of an aluminum-copper alloy.
 81. The imaging device according toclaim 77, wherein said interconnectors are formed of copper.
 82. Theimaging device according to claim 79, wherein said refractory metal istungsten.
 83. The imaging device according to claim 79, wherein saidrefractory metal is titanium.
 84. The imaging device according to claim72, wherein said self-aligned buried contact is formed between twotransistor gates.
 85. The imaging device according to claim 72, whereinsaid self-aligned buried contact is formed between two isolationregions.
 86. The imaging device according to claim 72, wherein saidself-aligned buried contact is formed between a transistor gate and anisolation region.
 87. The imaging device according to claim 84, furthercomprising an insulating layer formed over the gate of said transistorsand under the self-aligned buried contact.
 88. The imaging deviceaccording to claim 87, wherein said insulating layer includes a nitride.89. The imaging device according to claim 87, wherein said insulatinglayer includes an oxide.
 90. The imaging device according to claim 77,wherein said insulating layer is selected from a nitride, ONO, NO, ON orcombinations thereof.
 91. The imaging device according to claim 83,wherein said isolation region is a field oxide region.
 92. The imagingdevice according to claim 72, wherein said substrate is a semiconductorintegrated circuit substrate.
 93. A processing system comprising: (i) aprocessor; and (ii) a CMOS imaging device coupled to said processor andincluding: a substrate; a photosensitive area within said substrate foraccumulating photo-generated charge in said area; a readout circuitcomprising at least an output transistor formed on said substrate; and,a self-aligned buried contact formed over a doped region in saidsubstrate and between two structures on said substrate electricallyconnecting said imaging device, wherein said structures are selectedfrom a transistor gate and an isolation region.
 94. The system accordingto claim 93, wherein the accumulation of charge in said photosensitivearea is conducted by a photoconductor.
 95. The system according to claim93, wherein the accumulation of charge in said photosensitive area iscontrolled by a photogate.
 96. The system according to claim 93, whereinsaid photosensitive area is a photodiode.
 97. The system according toclaim 93, further including a charge transfer transistor and a resettransistor, wherein said self-aligned buried contact is aligned betweenthe gates of said charge transfer transistor and said reset transistor.98. The system according to claim 97, wherein said self-aligned buriedcontacts electrically connects said imaging device via interconnectors.99. The system according to claim 98, wherein said interconnectors areformed at least in part of doped polysilicon.
 100. The system accordingto claim 98, wherein said interconnectors are formed of at least onerefractory metal.
 101. The system according to claim 100, wherein saidrefractory metal is tungsten.
 102. The system according to claim 100,wherein said refractory metal is titanium.
 103. The system according toclaim 93, wherein said self-aligned buried contact is formed between twotransistor gates.
 104. The system according to claim 93, wherein saidself-aligned buried contact is formed between two isolation regions.105. The system according to claim 93, wherein said self-aligned buriedcontact is formed between a transistor gate and an isolation region.106. The system according to claim 103, further comprising an insulatinglayer formed over the gate of said transistors and under theself-aligned buried contact.
 107. The system according to claim 106,wherein said insulating layer includes a nitride.
 108. The systemaccording to claim 106, wherein said insulating layer includes an oxide.109. The system according to claim 106, wherein said insulating layer isselected from a nitride, ONO, NO, ON or combinations thereof.
 110. Thesystem according to claim 104, wherein said isolation region is a fieldoxide region.
 111. The system according to claim 93, wherein saidsubstrate is a semiconductor integrated circuit substrate.
 112. A methodof forming a self-aligned buried contact in a CMOS imager, comprisingthe steps of: providing a substrate including at least one transistorand at least one isolation region; forming an protective layer over saidsubstrate; selectively removing at least a portion of said protectivelayer between a gate of said at least one transistor and anothersubstrate feature selected from the group consisting of anothertransistor gate and said isolation region; forming a continuouslyconductive layer in said self-aligned plug opening to form aself-aligned buried contact.
 113. The method according to claim 112,wherein said self-aligned buried contact is formed between the gate ofsaid at least one transistor and the gate of said another transistor.114. The method according to claim 112, wherein said self-aligned buriedcontact is formed between two isolation regions.
 115. The methodaccording to claim 112, wherein said self-aligned buried contact isformed between said isolation region and the gate of said at least onetransistor.
 116. The method according to claim 113, further comprisingforming an insulating layer over the gate of said one and anothertransistor before said conductive layer formation.
 117. The methodaccording to claim 114, wherein said isolation region is a field oxideregion.
 118. The method according to claim 115, further comprisingforming an insulating layer over the gate of said transistor before saidconductive layer formation and wherein said isolation region is a fieldoxide region.
 119. The method according to claim 112, wherein saidprotective layer is selected from the group consisting of BPSG, PSG, BSGand undoped oxide.
 120. The method according to claim 112, wherein saidprotective layer is removed by selective etching.
 121. The methodaccording to claim 120, wherein said selective etching is dry etching.122. The method according to claim 110, wherein said insulating layerincludes a nitride.
 123. The method according to claim 116, wherein saidinsulating layer includes an oxide.
 124. The method according to claim122, wherein said insulating is selected from the group consisting ofnitride, ONO, NO and ON.
 125. The method according to claim 118, whereinsaid insulating layer includes a nitride.
 126. The method according toclaim 118, wherein said insulating layer includes an oxide.
 127. Themethod according to claim 125, wherein said insulating is selected fromthe group consisting of nitride, ONO, NO and ON.
 128. The methodaccording to claim 116, wherein said insulating layer is formed bychemical vapor deposition.
 129. The method according to claim 118,wherein said insulating layer is formed by chemical vapor deposition.130. The method according to claim 112, further comprising contactingsaid self-aligned buried contact with an electrical connector.
 131. Themethod according to claim 130, wherein said electrical connector isformed of a metal.
 132. The method according to claim 131, wherein saidelectrical connector is formed of a refractory metal.
 133. The methodaccording to claim 132, wherein said refractory metal includes tungstenand titanium.
 134. The method according to claim 130, wherein saidelectrical connector is formed of a doped polysilicon.
 135. The methodaccording to claim 130, wherein said electrical connector is formed ofan aluminum-copper alloy.
 136. The method according to claim 130,wherein said electrical connector is formed of copper.
 137. The methodaccording to claim 131, wherein said electrical connector furtherincludes a metal silicide formed over said doped polysilicon.
 138. Themethod according to claim 134, wherein said doped polysilicon is formedby chemical vapor deposition.
 139. The method according to claim 112,wherein said at least one transistor includes a transfer transistor andwherein said self-aligned buried contact is formed between an isolationregion and said transfer transistor.